This set deals with the memory elements of sequential logic. It covers SR latches built from NOR and NAND gates, gated D latches, JK, D and T flip-flops, characteristic equations, excitation tables, race-around and master-slave operation, flip-flop conversions, and timing parameters such as setup and hold time. It is aimed at GATE, university digital electronics papers and hardware interview rounds.
How to practise: read each question and tap the option you think is correct. You will see right away whether you got it, along with a short explanation, and your score is tracked at the bottom of the screen. This set has 18 questions.
Topics covered in this set
- NOR and NAND SR latches
- Gated D latch versus edge-triggered flip-flop
- Characteristic equations of JK, D and T
- Excitation tables
- Race-around and master-slave JK
- Flip-flop conversions
- Setup time, hold time and maximum clock frequency
Digital Electronics MCQs with answers and explanations
Q1. For an SR latch built from cross-coupled NOR gates, which input combination is not allowed?
a) S = 0, R = 0
b) S = 1, R = 0
c) S = 0, R = 1
d) S = 1, R = 1
Q2. For an SR latch built from cross-coupled NAND gates (active-low inputs), which input pair is not allowed?
a) S = 1, R = 1
b) S = 0, R = 1
c) S = 0, R = 0
d) S = 1, R = 0
Q3. What is the characteristic equation of a JK flip-flop?
a) Q+ = J + K'Q
b) Q+ = JK' + J'KQ
c) Q+ = JQ' + K'Q
d) Q+ = J ⊕ K ⊕ Q
Q4. Which equation gives the next state of a T flip-flop?
a) Q+ = TQ
b) Q+ = T + Q
c) Q+ = T'Q
d) Q+ = T ⊕ Q
Q5. According to the JK excitation table, what inputs are needed for the transition Q: 0 to 1?
a) J = X, K = 1
b) J = 1, K = 0
c) J = 1, K = X
d) J = 0, K = X
Q6. According to the SR excitation table, what inputs keep the output at 1 for the transition Q: 1 to 1?
a) S = 0, R = X
b) S = X, R = 0
c) S = 1, R = 0
d) S = X, R = 1
Q7. Race-around in a level-triggered JK flip-flop occurs when:
a) J = K = 0 and the clock is held low
b) the clock pulse width is shorter than the propagation delay
c) J = K = 1 and the clock pulse width exceeds the propagation delay
d) J and K are complements of each other
Q8. Which arrangement eliminates the race-around problem in a JK flip-flop?
a) Increasing the clock pulse width beyond the propagation delay
b) A master-slave JK flip-flop
c) Replacing NAND gates with NOR gates in the same level-triggered circuit
d) Tying both J and K permanently to logic 1
Q9. How is a JK flip-flop converted into a T flip-flop?
a) Connect J to T and K to T'
b) Connect J to T and K to Q
c) Connect J to Q' and K to T'
d) Connect J and K together and drive them with T
Q10. To make a D flip-flop behave as a T flip-flop, the D input should be driven by:
a) TQ
b) T + Q
c) T ⊕ Q
d) T'Q
Q11. To make a JK flip-flop behave as a D flip-flop, the inputs should be:
a) J = D, K = D'
b) J = D', K = D
c) J = D, K = D
d) J = D, K = Q
Q12. To convert an SR flip-flop into a JK flip-flop, the S and R inputs are driven by:
a) S = J, R = K
b) S = JQ', R = KQ
c) S = JQ, R = KQ'
d) S = J + Q, R = K + Q'
Q13. The setup time of a flip-flop is the:
a) minimum time the data input must remain stable after the clock edge
b) delay from the clock edge to the change in output
c) minimum width of the clock pulse
d) minimum time the data input must be stable before the active clock edge
Q14. A synchronous circuit has flip-flop clock-to-Q delay 6 ns, combinational logic delay 10 ns and setup time 4 ns. What is the maximum clock frequency?
a) 50 MHz
b) 62.5 MHz
c) 100 MHz
d) 40 MHz
Q15. A T flip-flop has T = 1 permanently and is clocked at 10 kHz. What is the frequency of its Q output?
a) 5 kHz
b) 10 kHz
c) 20 kHz
d) 2.5 kHz
Q16. What is the key difference between a latch and a flip-flop?
a) A latch stores two bits while a flip-flop stores one
b) A latch is level-sensitive while a flip-flop changes state only at a clock edge
c) A latch needs a clock while a flip-flop does not
d) A flip-flop is combinational while a latch is sequential
Q17. A negative-edge JK flip-flop starts with Q = 0. The (J, K) inputs on five successive edges are (1,0), (1,1), (0,0), (1,1), (0,1). What is Q after each edge?
a) 1, 0, 0, 1, 0
b) 1, 1, 1, 0, 0
c) 1, 0, 1, 0, 0
d) 0, 1, 1, 0, 0
Q18. Why does a gated D latch never enter the forbidden state of an SR latch?
a) It uses NOR gates instead of NAND gates
b) Its enable input is always held low
c) It has no feedback path between its gates
d) Its internal S and R inputs are driven by D and D', so they can never both be 1
Quick revision notes
- SR: Q+ = S + R'Q with SR = 0 (NOR latch: S = R = 1 forbidden; NAND latch: S' = R' = 0 forbidden).
- JK: Q+ = JQ' + K'Q; J = K = 1 toggles.
- D: Q+ = D; T: Q+ = T ⊕ Q.
- JK excitation: 0->0 (0,X), 0->1 (1,X), 1->0 (X,1), 1->1 (X,0).
- Race-around: level-triggered JK with J = K = 1 and clock width > propagation delay; fix with master-slave or edge triggering.
- Conversions: JK to T: J = K = T; D to T: D = T ⊕ Q; JK to D: J = D, K = D'.
- Tmin = tclk-Q + tcomb + tsetup; fmax = 1/Tmin.
- A T flip-flop with T = 1 divides the clock frequency by 2.
Frequently asked questions
What is the race-around condition in a JK flip-flop?
In a level-triggered JK flip-flop with J = K = 1, the output keeps toggling as long as the clock stays high if the pulse is longer than the propagation delay. The final state then becomes unpredictable.
What is an excitation table and how is it used?
An excitation table lists the flip-flop inputs required to produce each present-to-next state transition. It is used when designing counters and state machines to derive the input equations for each flip-flop.
What is the difference between setup time and hold time?
Setup time is how long the data must be stable before the clock edge, and hold time is how long it must remain stable after the edge. Violating either can cause metastability or a wrong value to be stored.
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