This final set links sequential design with hardware realities. It covers ripple and synchronous counters, mod-N design with reset logic, ring and Johnson counters, shift and universal registers, ROM and RAM capacity and chip expansion, and logic family parameters such as fan-out, noise margin, propagation delay and CMOS power. It suits GATE, university semester exams and core electronics interview rounds.
How to practise: read each question and tap the option you think is correct. You will see right away whether you got it, along with a short explanation, and your score is tracked at the bottom of the screen. This set has 18 questions.
Topics covered in this set
- Ripple versus synchronous counters
- Mod-N counters and reset logic
- Ring and Johnson counters
- Shift and universal shift registers
- ROM and RAM organisation and expansion
- TTL fan-out, noise margin and open-collector outputs
- Propagation delay and CMOS power
Digital Electronics MCQs with answers and explanations
Q1. A 4-bit ripple counter uses flip-flops with a propagation delay of 10 ns each. What is the maximum safe clock frequency if all outputs must settle within one clock period?
a) 100 MHz
b) 40 MHz
c) 25 MHz
d) 12.5 MHz
Q2. What is the minimum number of flip-flops needed to build a mod-25 counter?
a) 4
b) 5
c) 6
d) 25
Q3. How many valid states does a 5-bit Johnson (twisted-ring) counter cycle through?
a) 5
b) 10
c) 32
d) 31
Q4. How many unused states does a 4-bit ring counter have?
a) 8
b) 4
c) 0
d) 12
Q5. A mod-6 asynchronous counter is made from a 3-bit ripple up counter with an active-low clear. Which outputs feed the NAND gate that drives the clear input?
a) Q2 and Q0
b) Q1 and Q0
c) Q2 and Q1
d) Q2, Q1 and Q0
Q6. What is the main advantage of a synchronous counter over a ripple counter?
a) All flip-flops are clocked together, so propagation delays do not accumulate
b) It needs no logic gates between stages
c) It always uses fewer flip-flops
d) It can count only in one direction, which avoids glitches
Q7. A 4-bit shift-right register holds Q3Q2Q1Q0 = 1011, with serial data entering at Q3. What does it hold after two clock pulses with serial input 0?
a) 1100
b) 0101
c) 0010
d) 1110
Q8. Which operation can a universal shift register NOT perform by itself?
a) Parallel load
b) Shift left
c) Binary addition of two words
d) Shift right
Q9. A ROM has 12 address lines and 8 data lines. What is its storage capacity?
a) 12 KB
b) 4 KB
c) 8 KB
d) 32 KB
Q10. How many 1K x 4 RAM chips are needed to build an 8K x 8 memory?
a) 8
b) 32
c) 4
d) 16
Q11. Why does a DRAM need periodic refreshing while an SRAM does not?
a) DRAM cells use cross-coupled latches that lose state when clocked
b) DRAM is a non-volatile memory with limited write endurance
c) SRAM uses capacitors that never discharge
d) Each DRAM bit is stored as charge on a capacitor that leaks away
Q12. A logic gate has tPHL = 12 ns and tPLH = 8 ns. What is its average propagation delay?
a) 20 ns
b) 10 ns
c) 12 ns
d) 4 ns
Q13. A TTL gate has IOL = 16 mA, IOH = 400 µA, IIL = 1.6 mA and IIH = 40 µA. What is its fan-out?
a) 10
b) 20
c) 16
d) 40
Q14. A logic family has VOH = 2.7 V, VIH = 2.0 V, VOL = 0.5 V and VIL = 0.8 V. What is its low-level noise margin?
a) 0.3 V
b) 0.7 V
c) 1.2 V
d) 0.5 V
Q15. A CMOS gate drives a 50 pF load at 5 V with a switching frequency of 2 MHz. What is its dynamic power dissipation, using P = CV^2f?
a) 2.5 mW
b) 0.5 mW
c) 5 mW
d) 12.5 mW
Q16. Which of the following logic families is the fastest?
a) Standard TTL
b) 4000-series CMOS
c) RTL
d) ECL
Q17. Why does a TTL gate with an open-collector output need an external pull-up resistor?
a) To limit the current drawn by the totem-pole stage
b) To increase the fan-out to more than 100
c) To convert the gate into a tri-state output
d) The output transistor can only pull the line low, so a resistor is needed to produce a high level
Q18. A mod-8 synchronous up counter is built with T flip-flops Q2 Q1 Q0. What is the input expression for T2?
a) Q1Q0
b) Q1 + Q0
c) Q2Q1
d) Q0
Quick revision notes
- Ripple counter: delay = n x tpd, fmax = 1/(n x tpd); synchronous: fmax set by one stage plus gating.
- Mod-N needs ceil(log2 N) flip-flops.
- Ring counter: n states; Johnson counter: 2n states for n flip-flops.
- Memory with k address lines and n data lines: 2^k x n bits.
- Chips needed = (total words/chip words) x (total width/chip width).
- Fan-out = min(IOL/IIL, IOH/IIH); NML = VIL - VOL, NMH = VOH - VIH.
- Average tpd = (tPHL + tPLH)/2; CMOS dynamic power = C V^2 f.
- ECL is fastest; CMOS has lowest static power.
Frequently asked questions
What is the difference between a ring counter and a Johnson counter?
A ring counter feeds the last flip-flop output straight back to the first and has n states for n flip-flops. A Johnson counter feeds back the complemented output and gets 2n states from the same flip-flops.
How is fan-out of a logic gate calculated?
Fan-out is the number of similar gate inputs one output can drive without violating its logic levels. It is the smaller of IOL/IIL and IOH/IIH using the data-sheet currents.
Why is CMOS preferred in modern ICs?
CMOS draws almost no static current, so power is consumed mainly when switching, and it offers high noise margins and density. This makes it ideal for large, low-power VLSI chips.
Comments
Post a Comment