This set covers combinational circuit design. It includes half and full adders, subtractors, ripple-carry delay, carry look-ahead logic, multiplexers used as function generators, decoder and demultiplexer expansion, priority encoders, magnitude comparators, parity generators and static hazards. The questions mirror GATE, university semester exam and interview patterns where you must reason about circuit structure and timing, not just recall definitions.
How to practise: read each question and tap the option you think is correct. You will see right away whether you got it, along with a short explanation, and your score is tracked at the bottom of the screen. This set has 18 questions.
Topics covered in this set
- Half and full adders, half subtractors
- Ripple-carry delay and carry look-ahead
- Multiplexer trees and MUX-based function realisation
- Decoder expansion and demultiplexers
- Priority encoders and magnitude comparators
- Parity generators and static hazards
Digital Electronics MCQs with answers and explanations
Q1. The carry output of a full adder with inputs A, B and Cin can be written as:
a) A ⊕ B ⊕ Cin
b) AB + A'Cin
c) (A + B)Cin'
d) AB + Cin(A ⊕ B)
Q2. A full adder can be constructed from which combination of components?
a) Two half adders and one AND gate
b) One half adder and one XOR gate
c) Two half adders and one OR gate
d) Three half adders
Q3. For a half subtractor computing A - B, the borrow output is:
a) AB'
b) A ⊕ B
c) AB
d) A'B
Q4. A 16-bit ripple-carry adder uses full adders with carry delay 3 ns and sum delay 4 ns. What is the worst-case time for the most significant sum bit to settle?
a) 49 ns
b) 48 ns
c) 64 ns
d) 52 ns
Q5. In a carry look-ahead adder with Gi = AiBi and Pi = Ai ⊕ Bi, the carry C2 expressed in terms of C0 is:
a) G1 + P1G0 + P1P0C0
b) G1 + P1C0
c) G0 + P0G1 + P1P0C0
d) P1 + G1G0 + G1G0C0
Q6. How many select lines does a 32-to-1 multiplexer need?
a) 4
b) 5
c) 6
d) 32
Q7. F(A,B,C) = Σm(1,2,6,7) is implemented on a 4-to-1 MUX with A and B on the select lines (A as MSB). What are the data inputs I0, I1, I2, I3?
a) C', C, 0, 1
b) C, C', 0, 1
c) C, C', 1, 0
d) C, C, 0, 1
Q8. What is the minimum number of 4-to-1 multiplexers needed to build a 16-to-1 multiplexer?
a) 4
b) 5
c) 6
d) 8
Q9. How many 3-to-8 decoders with an enable input are needed to build a 6-to-64 decoder in a tree arrangement?
a) 8
b) 16
c) 10
d) 9
Q10. A 4-input priority encoder gives D3 the highest priority. If the inputs D3 D2 D1 D0 = 0110, what is the 2-bit output?
a) 01
b) 10
c) 11
d) 00
Q11. What problem does a priority encoder solve compared with a simple binary encoder?
a) It gives a defined output when more than one input is active at once
b) It reduces the number of output lines
c) It converts binary outputs into one-hot form
d) It removes the need for an enable input
Q12. In a 1-bit magnitude comparator, the output indicating A > B is:
a) A'B
b) A ⊕ B
c) AB'
d) (A ⊕ B)'
Q13. For 2-bit numbers A1A0 and B1B0, the equality output of a magnitude comparator is:
a) (A1 ⊕ B1)(A0 ⊕ B0)
b) (A1 XNOR B1) + (A0 XNOR B0)
c) (A1 XNOR B1)(A0 XNOR B0)
d) A1B1 + A0B0
Q14. A decoder with an enable input can be used as a demultiplexer when:
a) the outputs are tied together through an OR gate
b) all inputs are held at logic 1
c) the enable input is permanently grounded
d) the enable input carries the data and the inputs act as select lines
Q15. In a 4-bit binary adder-subtractor, what happens when the mode input M is set to 1?
a) Each B bit is inverted through XOR gates and the carry-in is set to 1, so the circuit computes A - B
b) The adder is disabled and outputs zero
c) A and B are swapped, so the circuit computes B - A
d) Only the carry-in is set to 1, so the circuit computes A + B + 1
Q16. What is the output P of an odd-parity generator for the 3-bit data A, B, C?
a) A ⊕ B ⊕ C
b) ABC
c) (A ⊕ B ⊕ C)'
d) A + B + C
Q17. The circuit F = AB + A'C has a static-1 hazard when A changes while B = C = 1. Which term should be added to remove it?
a) BC
b) AC
c) A'B
d) B'C'
Q18. A 2-to-1 multiplexer has select input A, data input I0 = 0 and I1 = B. Which function does it realise?
a) A + B
b) A ⊕ B
c) A'B
d) AB
Quick revision notes
- Half adder: S = A ⊕ B, C = AB. Full adder: S = A ⊕ B ⊕ Cin, Cout = AB + Cin(A ⊕ B).
- Half subtractor: D = A ⊕ B, Borrow = A'B.
- Ripple-carry worst case ~ (n-1) x carry delay + sum delay.
- CLA: Gi = AiBi, Pi = Ai ⊕ Bi, C(i+1) = Gi + PiCi.
- 2^n-to-1 MUX needs n select lines; a MUX with n selects can realise any (n+1)-variable function.
- Decoder + OR gates realise any SOP; decoder with enable = demultiplexer.
- Equality comparator: AND of bit-wise XNORs.
- Static hazards are removed by adding redundant consensus terms.
Frequently asked questions
Why is a carry look-ahead adder faster than a ripple-carry adder?
A ripple-carry adder waits for each carry to pass through every stage, so delay grows linearly with word length. A carry look-ahead adder computes all carries in parallel from the generate and propagate signals, so delay stays almost constant for a block.
What is the difference between a multiplexer and a demultiplexer?
A multiplexer selects one of many inputs and sends it to a single output, while a demultiplexer sends a single input to one of many outputs. Both use select lines to choose the path.
How can a multiplexer implement any Boolean function?
Connect some variables to the select lines and feed each data input with 0, 1 or a function of the remaining variable. A 2^n-to-1 MUX can implement any function of n + 1 variables this way.
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