Computer Organization and Digital Logic together carry steady marks in GATE CSE, and most questions are short calculations. This GATE-style set covers cache address breakdown, average memory access time, pipeline speedup and hazards, number representation, K-map simplification and sequential circuits.
How to practise: read each question and tap the option you think is correct. You will see right away whether you got it, along with a short explanation, and your score is tracked at the bottom of the screen. This set has 15 questions.
Topics covered in this set
- Direct-mapped and set-associative cache addressing
- Average memory access time
- Pipeline cycles, speedup and hazards
- Addressing modes, IEEE 754 and two's complement
- K-maps, universal gates and multiplexers
- Flip-flops, counters and DMA
GATE CSE COA and Digital Logic MCQs with answers and explanations
Q1. A 32 KB direct-mapped cache has 64-byte blocks and the machine uses 32-bit byte addresses. How are the address bits split into tag, index and offset?
a) Tag 17, index 9, offset 6
b) Tag 20, index 6, offset 6
c) Tag 17, index 6, offset 9
d) Tag 15, index 11, offset 6
Q2. A 32 KB 4-way set-associative cache has 64-byte blocks and the machine uses 32-bit byte addresses. How many tag bits are there?
a) 17
b) 18
c) 19
d) 21
Q3. A cache has a hit time of 1 ns, a miss rate of 5% and a miss penalty of 100 ns. What is the average memory access time?
a) 5 ns
b) 10 ns
c) 6 ns
d) 100 ns
Q4. How many clock cycles does a 5-stage pipeline need to execute 100 instructions with no stalls?
a) 105
b) 104
c) 100
d) 500
Q5. A 5-stage pipeline executes 100 instructions with no stalls. What is the speedup over a non-pipelined machine that takes 5 cycles per instruction (same clock)?
a) 4.81
b) 5.00
c) 4.50
d) 1.04
Q6. Which technique reduces stalls caused by a data dependency between consecutive instructions?
a) Adding more registers to the ISA
b) Branch prediction
c) Operand forwarding (bypassing)
d) Increasing cache size
Q7. In which addressing mode is the operand value itself part of the instruction?
a) Register indirect
b) Direct
c) Immediate
d) Indirect
Q8. In IEEE 754 single precision, how many exponent bits are there and what is the bias?
a) 8 bits, bias 127
b) 11 bits, bias 1023
c) 8 bits, bias 128
d) 7 bits, bias 63
Q9. What range of integers can an 8-bit two's complement number represent?
a) −127 to 127
b) 0 to 255
c) −256 to 255
d) −128 to 127
Q10. What is the minimal expression for F(A, B, C) = Σm(0, 2, 4, 6)?
a) C'
b) B'
c) A'
d) A'C'
Q11. Which gate is called universal because any Boolean function can be built using only that gate?
a) OR
b) NAND
c) AND
d) XOR
Q12. How many select lines does a 16-to-1 multiplexer need?
a) 2
b) 4
c) 8
d) 16
Q13. What does a JK flip-flop do on a clock edge when J = 1 and K = 1?
a) Sets to 1
b) Holds its state
c) Resets to 0
d) Toggles its output
Q14. What is the minimum number of flip-flops needed for a mod-10 counter?
a) 3
b) 5
c) 10
d) 4
Q15. Direct Memory Access (DMA) is used to:
a) Transfer blocks of data between I/O devices and memory without the CPU handling each word
b) Replace the cache
c) Speed up the ALU
d) Execute interrupts faster
Quick revision notes
- Offset = log₂(block size); index = log₂(lines or sets); tag = rest.
- AMAT = hit time + miss rate × penalty.
- Pipeline cycles = k + n − 1.
- IEEE 754 single: 1 + 8 (bias 127) + 23 bits.
- n flip-flops give up to 2ⁿ counter states.
Frequently asked questions
Are these GATE previous year questions?
No. They are original GATE-style questions on COA and Digital Logic.
What is the most common cache mistake?
Forgetting that index bits count sets, not lines, in a set-associative cache. Divide the number of lines by the associativity first.
Is pipeline speedup always equal to the number of stages?
Only in the ideal limit. Fill time, stalls and unequal stage delays reduce it.
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